View M5M29KB641AVP_5605710.PDF datasheet online --- IC-ON-LINE

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m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 1 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory pin configuration (top view) outline 48p3r - c digital cellar phone, telecommunication, pda, car navigation system, video game machine 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rp# a21 ry/by# a18 a17 a7 a6 a5 a4 a3 a16 byte# gnd dq15/a - 1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# gnd 28 25 a0 24 a2 a1 20.0 mm 12.0 mm wp# description features access time flash 70ns (max.) supply voltage vcc= 3.0 ~ 3.6v ambient temperature ta= - 40 ~ 85 c package 48pin tsop(type - i), lead pitch 0.5mm outer - lead finishing : sn - cu application vcc : vcc gnd : gnd a0 - a21 : address dq0 - dq15 : data i/o ce# : chip enable oe# : output enable we# : write enable wp# : write protect rp# : reset power down byte# : byte enable ry/by# : ready/busy ce# the m5m29kb/t641avp are 3.3v - only high speed 67,108,864 - bit cmos boot block flash memories with alternating bgo(back ground operation) feature. the bgo feature of the device allows program or erase operations to be performed in one bank while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for mobile and personal computing, and communication products. the m5m29kb/t641avp are fabricated by cmos technology for the peripheral circuit and dinor iv(divided bit - line nor iv) architecture for the memory cell, and are available in 48pin tsop(i) for lead free use. m5m29kb/t641avp provides for software lock release function. usually, all memory blocks are locked and can not be programmed or erased, when wp# is low. using software lock release function, program or erase operation can be executed. 27 26 m5m29kb/t641avp
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 2 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory 64 m flash memory block diagram a0 to a21 oe# we# wp# rp# dq0 to dq15 64 mbit dinor iv flash memory vcc gnd ce# capacitance min. typ. max. cin input capacitance a21-a0, oe#, we#, ce#, wp#, rp#,byte# 12 pf cout output capacitance dq15-dq0,ry/by# 12 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter byte# ry/by#
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 3 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory the 64m - bit dinor iv(divided bit line nor iv) flash memory is 3.3v - only high speed 67,108,864 - bit cmos boot block flash memory. alternating bgo(back ground operation) feature of the device allows program or erase operations to be performed in one bank while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for communication products and cellular phone.the flash memory is fabricated by cmos technology for the peripheral circuits and dinor iv architecture for the memory cells. features - organization 4,194,304 - word x 16 - bit 8,388,608 - word x 8 - bit - supply voltage vcc = 3.0 ~ 3.6v - access time random access 70ns(max.) random page read 25ns(max.) read 108mw (max. at 5mhz) (after automatic power down) 0.33 w(typ.) - program/erase 126mw(max.) standby 0.33 w(typ.) deep power down mode 0.33 w(typ.) - auto program for bank(i) ? bank(iv) program time word program 30 s/1word(typ.) byte program 30 s/1byte(typ.) page program 4ms(typ.) program unit word program 1 word byte program 1 byte page program 128 words/256 bytes - auto erase erase time 150ms(typ.) erase unit bank(i) boot block 4k - word /8k - byte x 2 parameter block 4k - word /8k - byte x 6 main block 32k - word /64k - byte x 7 bank(ii) main block 32k - word /64k - byte 8 bank(iii) main block 32k - word /64k - byte x 56 bank(iv) main block 32k - word /64k - byte x 56 - program/erase cycles 100kcycles - boot block bottom boot m***b6****** top boot m***t6****** - the other functions software command control quick data reclaim software lock release(while wp# is low) erase suspend/resume program suspend/resume status register read alternating back ground program/erase operation between bank(i), bank(ii), bank(iii) and bank(iv) random page read flash memory part description
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 4 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block diagram (64mbit flash memory) main block 134 32k-word bank(iv) 56 blocks main block 79 32k-word main block 78 32k-word bank(iii) 56 blocks main block 23 32k-word main block 22 32k-word bank(ii) 8 blocks main block 15 32k-word main block 14 32k-word main block 8 32k-word bank(i) parameter block 7 4k-word 15 blocks parameter block 2 4k-word boot block 1 4k-word boot block 0 4k-word x-decoder 128-word page buffer y-decoder y-gate / sense amp. address input status / id register multiplexer command user interface write state machine i/o buffer data i/o a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ce# oe# we# wp# rp# dq0 dq1 dq15 /a-1 dq14 vcc gnd chip enable output enable write enable write protect reset / powerdown a21 by te# byte# ry/ by# ready / busy
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 5 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory when rp# is at vil, the device is in the deep power down mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high - impedance (high - z) state. after return from power down, the cui is reset to read array, and the status register is cleared to value 80h. during block erase or program modes, rp# low will abort either operation. memory array data of the block being altered become invalid. the automatic power down minimizes the power consumption during read mode. the device automatically turns to this mode when any addresses or ce# isn't changed more than 200ns after the last alternation. the power consumption becomes the same as the stand - by mode. during this mode, the output data is latched and can be read out. new data is read out correctly when addresses are changed. in the 64m - bit dinor iv flash memory , when one memory address is read according to a read mode in the case of the same as an access when a read mode command is input, an another bank memory data can be read out (read array or page read) by changing an another bank address. when oe# is at vih, output from the devices is disabled. data input/output are in a high - impedance (high - z) state. output disable the 64m - bit dinor iv flash memory includes on - chip program/erase control circuitry. the write state machine (wsm) controls block erase and word/page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep power down mode is enabled when the rp# pin is at gnd, minimizing power consumption. function of flash memory the 64m - bit dinor iv flash memory has four read modes, which accesses to the memory array ,the page read, the device identifier and the status register. the appropriate read commands are required to be written to the cui. upon initial device power up or after exit from deep power down, the 64m - bit dinor iv flash memory automatically resets to read array mode. in the read array mode and in the conditions are low level input to oe#, high level input to we# and rp#, low level input to ce# and address signals to the address inputs (a21 - a0:word mode, a21 - a - 1:byte mode) the data of the addressed location to the data input/output (dq15 - dq0:word mode, dq7 - dq0:byte mode) is output. read writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing we# to low level and oe# is at high level, while ce# is at low level. address and data are latched on the earlier rising edge of we# and ce#. standard micro processor write timings are used. write the 64m - bit dinor iv flash memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. array read operation with the other bank in bgo is performed by changing the bank address without any additional command. when the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. the access time with bgo is the same as the normal read operation. bgo must be between bank(i), bank(ii), bank(iii) and bank(iv). when ce# is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high - impedance (high - z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes. standby alternating background operation (bgo) deep power down bbr(back bank array read) automatic power down (auto - pd)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 6 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory we can normally read device identifier codes when read device identifier code command (90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from a0 address 0h and 1h in a bank address, respectively. the device is in read array mode on initial device power up and after exit from deep power down, or by writing ffh to the command user interface. after starting the internal operation the device is set to the read status register mode automatically. automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. page program allows fast programming of 128words of data. writing of 41h initiates the page program operation for the data area. from 2nd cycle to 129th cycle, write data must be serially inputted. address a6 - a0 have to be incremented from 00h to 7fh. after completion of data loading, the wsm controls the program pulse application and verify operation. single data load to the page buffer is performed by writing 74h followed by a second write specifying the column address and data. distinct data up to 128word can be loaded to the page buffer by this two - command sequence. on the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing page buffer to flash command of 0eh followed by the confirm command of d0h. after completion of programming the data on the page buffer is cleared automatically. the device operations are selected by writing specific software command into the command user interface. software command definitions the status register is read after writing the read status register command of 70h to the command user interface. also, after starting the internal operation the device is set to the read status register mode automatically. the contents of status register are latched on the later falling edge of oe# must be toggled every status read. the erase status, program status and block status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicate various failure conditions. block erase / confirm command (20h/d0h) clear status register command (50h) read array command (ffh) read status register command (70h) read device identifier command (90h) b) page program for data blocks (41h) c) single data load to page buffer (74h) / page buffer to flash (0eh/d0h) word/byte program is executed by a two - command sequence. the word/byte program setup command of 40h is written to the command interface, followed by a second write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. a) word / byte program (40h) program commands the page read command (f3h) timing can be used by writing the first command to cui and f - ce# falls vil or changing the address(a21 - a2) is necessary to start activating page read mode. this command is fast random 4 words read. during the read it is necessary to fix f - ce# low and change addresses that are defined by a0 and a1(0h - 3h) at random continuously. the mode is kept until f - rp# is set to l or this chip is powered down. the first read of page read timing is the same as normal read (ta(ce)). f - ce# should be fallen ? l ? . the read timing after the first is the same as ta(pad). in the page read mode the upper address(a21 - a2) or f - ce# are supposed not to be clocked during read operation. otherwise the access time is as same as normal read. page read command (f3h)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 7 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory loaded data to the page buffer is cleared by writing the clear page buffer command of 55h followed by the confirm command of d0h. this command is valid for clearing data loaded by single data load to page buffer command. writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the bank address is required when writing the suspend/resume command. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes. the 64m - bit dinor iv flash memory has a master write protect pin (wp#). when wp# is at vih, all blocks can be programmed or erased. when wp# is low, all blocks are in locked mode which prevents any modifications to memory blocks. software lock release function is only command which allows to program or erase. when the power supply voltage is less than vlko, low vcc lock - out voltage, the device is set to the read - only mode. a delay time of 60 s is required before any device operation is initiated. the delay time is measured from the time flash vcc reaches flash vccmin (3.0v). during power up, rp# = gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. array data load to the page buffer is performed by writing the flash to page buffer command of f1h followed by the confirm command of d0h. an address within the page to be loaded is required. then the array data can be copied into the other pages within the same bank by using the page buffer to flash command. flash to page buffer command (f1h/d0h) the 64m - bit dinor iv flash memory is constructed by 2 boot blocks of 4k words, 6 parameter blocks of 4k words and 7 main blocks of 32k words in bank(i), by 8 main blocks of 32k words in bank(ii) and by 56 main blocks of 32k words in bank(iii) and bank(iv). power supply voltage clear page buffer command (55h/d0h) data protection suspend/resume command (b0h/d0h) memory organization the command sequence enable us to erase all blocks. the command can be used by writing setup command a7h(1 st cycle) and confirm command d0h(2 nd cycle). the sequence is not valid in case of wp#=vil. erase all unlocked blocks command (a7h/d0h)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 8 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block organization 64 m - bit dinor(iv) flash memory map (bottom boot) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) 1a0000h- 1affffh d0000h- d7fffh 32kword 33 3c0000h- 3cffffh 1e0000h- 1e7fffh 32kword 67 5e0000h- 5effffh 2f0000h- 2f7fffh 32kword 101 7f0000h- 7fffffh 3f8000h- 3fffffh 32kword 134 190000h- 19ffffh c8000h- cffffh 32kword 32 3b0000h- 3bffffh 1d8000h- 1dffffh 32kword 66 5d0000h- 5dffffh 2e8000h- 2effffh 32kword 100 7e0000h- 7effffh 3f0000h- 3f7fffh- 32kword 133 180000h- 18ffffh c0000h- c7fffh 32kword 31 3a0000h- 3affffh 1d0000h- 1d7fffh 32kword 65 5c0000h- 5cffffh 2e0000h- 2e7fffh 32kword 99 7d0000h- 7dffffh 3e8000h- 3effffh 32kword 132 170000h- 17ffffh b8000h- bffffh 32kword 30 390000h- 39ffffh 1c8000h- 1cffffh 32kword 64 5b0000h- 5bffffh 2d8000h- 2dffffh 32kword 98 7c0000h- 7cffffh 3e0000h- 3e7fffh- 32kword 131 160000h- 16ffffh b0000h- b7fffh 32kword 29 380000h- 38ffffh 1c0000h- 1c7fffh 32kword 63 5a0000h- 5affffh 2d0000h- 2d7fffh 32kword 97 7b0000h- 7bffffh 3d8000h- 3dffffh 32kword 130 150000h- 15ffffh a8000h- affffh 32kword 28 370000h- 37ffffh 1b8000h- 1bffffh 32kword 62 590000h- 59ffffh 2c8000h- 2cffffh 32kword 96 7a0000h- 7affffh 3d0000h- 3d7fffh- 32kword 129 140000h- 14ffffh a0000h- a7fffh 32kword 27 360000h- 36ffffh 1b0000h- 1b7fffh 32kword 61 580000h- 58ffffh 2c0000h- 2c7fffh 32kword 95 790000h- 79ffffh 3c8000h- 3cffffh 32kword 128 130000h- 13ffffh 98000h- 9ffffh 32kword 26 350000h- 35ffffh 1a8000h- 1affffh 32kword 60 570000h- 57ffffh 2b8000h- 2bffffh 32kword 94 780000h- 78ffffh 3c0000h- 3c7fffh- 32kword 127 120000h- 12ffffh 90000h- 97fffh 32kword 25 340000h- 34ffffh 1a0000h- 1a7fffh 32kword 59 560000h- 56ffffh 2b0000h- 2b7fffh 32kword 93 770000h- 77ffffh 3b8000h- 3bffffh 32kword 126 110000h- 11ffffh 88000h- 8ffffh 32kword 24 330000h- 33ffffh 198000h- 19ffffh 32kword 58 550000h- 55ffffh 2a8000h- 2affffh 32kword 92 760000h- 76ffffh 3b0000h- 3b7fffh- 32kword 125 100000h- 10ffffh 80000h- 87fffh 32kword 23 320000h- 32ffffh 190000h- 197fffh 32kword 57 540000h- 54ffffh 2a0000h- 2a7fffh 32kword 91 750000h- 75ffffh 3a8000h- 3affffh 32kword 124 f0000h- fffffh 78000h- 7ffffh 32kword 22 310000h- 31ffffh 188000h- 18ffffh 32kword 56 530000h- 53ffffh 298000h- 29ffffh 32kword 90 740000h- 74ffffh 3a0000h- 3a7fffh- 32kword 123 e0000h- effffh 70000h- 77fffh 32kword 21 300000h- 30ffffh 180000h- 187fffh 32kword 55 520000h- 52ffffh 290000h- 297fffh 32kword 89 730000h- 73ffffh 398000h- 39ffffh 32kword 122 d0000h- dffffh 68000h- 6ffffh 32kword 20 2f0000h- 2fffffh 178000h- 17ffffh 32kword 54 510000h- 51ffffh 288000h- 28ffffh 32kword 88 720000h- 72ffffh 390000h- 397fffh- 32kword 121 c0000h- cffffh 60000h- 67fffh 32kword 19 2e0000h- 2effffh 170000h- 177fffh 32kword 53 500000h- 50ffffh 280000h- 287fffh 32kword 87 710000h- 71ffffh 388000h- 38ffffh 32kword 120 b0000h- bffffh 58000h- 5ffffh 32kword 18 2d0000h- 2dffffh 168000h- 16ffffh 32kword 52 4f0000h- 4fffffh 278000h- 27ffffh 32kword 86 700000h- 70ffffh 380000h- 387fffh- 32kword 119 a0000h- affffh 50000h- 57fffh 32kword 17 2c0000h- 2cffffh 160000h- 167fffh 32kword 51 4e0000h- 4effffh 270000h- 277fffh 32kword 85 6f0000h- 6fffffh 378000h- 37ffffh 32kword 118 90000h- 9ffffh 48000h- 4ffffh 32kword 16 2b0000h- 2bffffh 158000h- 15ffffh 32kword 50 4d0000h- 4dffffh 268000h- 26ffffh 32kword 84 6e0000h- 6effffh 370000h- 377fffh- 32kword 117 80000h- 8ffffh 40000h- 47fffh 32kword 15 2a0000h- 2affffh 150000h- 157fffh 32kword 49 4c0000h- 4cffffh 260000h- 267fffh 32kword 83 6d0000h- 6dffffh 368000h- 36ffffh 32kword 116 70000h- 7ffffh 38000h- 3ffffh 32kword 14 290000h- 29ffffh 148000h- 14ffffh 32kword 48 4b0000h- 4bffffh 258000h- 25ffffh 32kword 82 6c0000h- 6cffffh 360000h- 367fffh- 32kword 115 60000h- 6ffffh 30000h- 37fffh 32kword 13 280000h- 28ffffh 140000h- 147fffh 32kword 47 4a0000h- 4affffh 250000h- 257fffh 32kword 81 6b0000h- 6bffffh 358000h- 35ffffh 32kword 114 50000h- 5ffffh 28000h- 2ffffh 32kword 12 270000h- 27ffffh 138000h- 13ffffh 32kword 46 490000h- 49ffffh 248000h- 24ffffh 32kword 80 6a0000h- 6affffh 350000h- 357fffh- 32kword 113 40000h- 4ffffh 20000h- 27fffh 32kword 11 260000h- 26ffffh 130000h- 137fffh 32kword 45 480000h- 48ffffh 240000h- 247fffh 32kword 79 690000h- 69ffffh 348000h- 34ffffh 32kword 112 30000h- 3ffffh 18000h- 1ffffh 32kword 10 250000h- 25ffffh 128000h- 12ffffh 32kword 44 470000h- 47ffffh 238000h- 23ffffh 32kword 78 680000h- 68ffffh 340000h- 347fffh- 32kword 111 20000h- 2ffffh 10000h- 17fffh 32kword 9 240000h- 24ffffh 120000h- 127fffh 32kword 43 460000h- 46ffffh 230000h- 237fffh 32kword 77 670000h- 67ffffh 338000h- 33ffffh 32kword 110 10000h- 1ffffh 08000h- 0ffffh 32kword 8 230000h- 23ffffh 118000h- 11ffffh 32kword 42 450000h- 45ffffh 228000h- 22ffffh 32kword 76 660000h- 66ffffh 330000h- 337fffh- 32kword 109 0e000h- 0ffffh 07000h- 07fffh 4kword 7 220000h- 22ffffh 110000h- 117fffh 32kword 41 440000h- 44ffffh 220000h- 227fffh 32kword 75 650000h- 65ffffh 328000h- 32ffffh 32kword 108 0c000h- 0dfffh 06000h- 06fffh 4kword 6 210000h- 21ffffh 108000h- 10ffffh 32kword 40 430000h- 43ffffh 218000h- 21ffffh 32kword 74 640000h- 64ffffh 320000h- 327fffh- 32kword 107 0a000h- 0bfffh 05000h- 05fffh 4kword 5 200000h- 20ffffh 100000h- 107fffh 32kword 39 420000h- 42ffffh 210000h- 217fffh 32kword 73 630000h- 63ffffh 318000h- 31ffffh 32kword 106 08000h- 09fffh 04000h- 04fffh 4kword 4 1f0000h- 1fffffh f8000h- fffffh 32kword 38 410000h- 41ffffh 208000h- 20ffffh 32kword 72 620000h- 62ffffh 310000h- 317fffh- 32kword 105 06000h- 07fffh 03000h- 03fffh 4kword 3 1e0000h- 1effffh f0000h- f7fffh 32kword 37 400000h- 40ffffh 200000h- 207fffh 32kword 71 610000h- 61ffffh 308000h- 30ffffh 32kword 104 04000h- 05fffh 02000h- 02fffh 4kword 2 1d0000h- 1dffffh e8000h- effffh 32kword 36 3f0000h- 3fffffh 1f8000h- 1fffffh 32kword 70 600000h- 60ffffh 300000h- 307fffh- 32kword 103 02000h- 03fffh 01000h- 01fffh 4kword 1 1c0000h- 1cffffh e0000h- e7fffh 32kword 35 3e0000h- 3effffh 1f0000h- 1f7fffh 32kword 69 5f0000h- 5fffffh 2f8000h- 2fffffh 32kword 102 00000h- 01fffh 00000h- 00fffh 4kword 0 1b0000h- 1bffffh d8000h- dffffh 32kword 34 3d0000h- 3dffffh 1e8000h- 1effffh 32kword 68 a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) bank(iii) bank(iii) bank(i) bank(ii) bank(iii) bank(iv) bank(iv)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 9 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block organization 64 m - bit dinor(iv) flash memory map (top boot) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) 210000h- 21ffffh 108000h- 10ffffh 32kword 33 430000h- 43ffffh 218000h- 21ffffh 32kword 67 650000h- 65ffffh 328000h- 32ffffh 32kword 101 7fe000h- 7fffffh 3ff000h- 3fffffh 4kword 134 200000h- 20ffffh 100000h- 107fffh 32kword 32 420000h- 42ffffh 210000h- 217fffh 32kword 66 640000h- 64ffffh 320000h- 327fffh 32kword 100 7fc000h- 7fdfffh 3fe000h- 3fefffh 4kword 133 1f0000h- 1fffffh f8000h- fffffh 32kword 31 410000h- 41ffffh 208000h- 20ffffh 32kword 65 630000h- 63ffffh 318000h- 31ffffh 32kword 99 7fa000h- 7fbfffh 3fd000h- 3fdfffh 4kword 132 1e0000h- 1effffh f0000h- f7fffh 32kword 30 400000h- 40ffffh 200000h- 207fffh 32kword 64 620000h- 62ffffh 310000h- 317fffh 32kword 98 7f8000h- 7f9fffh 3fc000h- 3fcfffh 4kword 131 1d0000h- 1dffffh e8000h- effffh 32kword 29 3f0000h- 3fffffh 1f8000h- 1fffffh 32kword 63 610000h- 61ffffh 308000h- 30ffffh 32kword 97 7f6000h- 7f7fffh 3fb000h- 3fbfffh 4kword 130 1c0000h- 1cffffh e0000h- e7fffh 32kword 28 3e0000h- 3effffh 1f0000h- 1f7fffh 32kword 62 600000h- 60ffffh 300000h- 307fffh 32kword 96 7f4000h- 7f5fffh 3fa000h- 3fafffh 4kword 129 1b0000h- 1bffffh d8000h- dffffh 32kword 27 3d0000h- 3dffffh 1e8000h- 1effffh 32kword 61 5f0000h- 5fffffh 2f8000h- 2fffffh 32kword 95 7f2000h- 7f3fffh 3f9000h- 3f9fffh 4kword 128 1a0000h- 1affffh d0000h- d7fffh 32kword 26 3c0000h- 3cffffh 1e0000h- 1e7fffh 32kword 60 5e0000h- 5effffh 2f0000h- 2f7fffh 32kword 94 7f0000h- 7f1fffh 3f8000h- 3f8fffh 4kword 127 190000h- 19ffffh c8000h- cffffh 32kword 25 3b0000h- 3bffffh 1d8000h- 1dffffh 32kword 59 5d0000h- 5dffffh 2e8000h- 2effffh 32kword 93 7e0000h- 7effffh 3f0000h- 3f7fffh- 32kword 126 180000h- 18ffffh c0000h- c7fffh 32kword 24 3a0000h- 3affffh 1d0000h- 1d7fffh 32kword 58 5c0000h- 5cffffh 2e0000h- 2e7fffh 32kword 92 7d0000h- 7dffffh 3e8000h- 3effffh 32kword 125 170000h- 17ffffh b8000h- bffffh 32kword 23 390000h- 39ffffh 1c8000h- 1cffffh 32kword 57 5b0000h- 5bffffh 2d8000h- 2dffffh 32kword 91 7c0000h- 7cffffh 3e0000h- 3e7fffh- 32kword 124 160000h- 16ffffh b0000h- b7fffh 32kword 22 380000h- 38ffffh 1c0000h- 1c7fffh 32kword 56 5a0000h- 5affffh 2d0000h- 2d7fffh 32kword 90 7b0000h- 7bffffh 3d8000h- 3dffffh 32kword 123 150000h- 15ffffh a8000h- affffh 32kword 21 370000h- 37ffffh 1b8000h- 1bffffh 32kword 55 590000h- 59ffffh 2c8000h- 2cffffh 32kword 89 7a0000h- 7affffh 3d0000h- 3d7fffh- 32kword 122 140000h- 14ffffh a0000h- a7fffh 32kword 20 360000h- 36ffffh 1b0000h- 1b7fffh 32kword 54 580000h- 58ffffh 2c0000h- 2c7fffh 32kword 88 790000h- 79ffffh 3c8000h- 3cffffh 32kword 121 130000h- 13ffffh 98000h- 9ffffh 32kword 19 350000h- 35ffffh 1a8000h- 1affffh 32kword 53 570000h- 57ffffh 2b8000h- 2bffffh 32kword 87 780000h- 78ffffh 3c0000h- 3c7fffh- 32kword 120 120000h- 12ffffh 90000h- 97fffh 32kword 18 340000h- 34ffffh 1a0000h- 1a7fffh 32kword 52 560000h- 56ffffh 2b0000h- 2b7fffh 32kword 86 770000h- 77ffffh 3b8000h- 3bffffh 32kword 119 110000h- 11ffffh 88000h- 8ffffh 32kword 17 330000h- 33ffffh 198000h- 19ffffh 32kword 51 550000h- 55ffffh 2a8000h- 2affffh 32kword 85 760000h- 76ffffh 3b0000h- 3b7fffh- 32kword 118 100000h- 10ffffh 80000h- 87fffh 32kword 16 320000h- 32ffffh 190000h- 197fffh 32kword 50 540000h- 54ffffh 2a0000h- 2a7fffh 32kword 84 750000h- 75ffffh 3a8000h- 3affffh 32kword 117 f0000h- fffffh 78000h- 7ffffh 32kword 15 310000h- 31ffffh 188000h- 18ffffh 32kword 49 530000h- 53ffffh 298000h- 29ffffh 32kword 83 740000h- 74ffffh 3a0000h- 3a7fffh- 32kword 116 e0000h- effffh 70000h- 77fffh 32kword 14 300000h- 30ffffh 180000h- 187fffh 32kword 48 520000h- 52ffffh 290000h- 297fffh 32kword 82 730000h- 73ffffh 398000h- 39ffffh 32kword 115 d0000h- dffffh 68000h- 6ffffh 32kword 13 2f0000h- 2fffffh 178000h- 17ffffh 32kword 47 510000h- 51ffffh 288000h- 28ffffh 32kword 81 720000h- 72ffffh 390000h- 397fffh- 32kword 114 c0000h- cffffh 60000h- 67fffh 32kword 12 2e0000h- 2effffh 170000h- 177fffh 32kword 46 500000h- 50ffffh 280000h- 287fffh 32kword 80 710000h- 71ffffh 388000h- 38ffffh 32kword 113 b0000h- bffffh 58000h- 5ffffh 32kword 11 2d0000h- 2dffffh 168000h- 16ffffh 32kword 45 4f0000h- 4fffffh 278000h- 27ffffh 32kword 79 700000h- 70ffffh 380000h- 387fffh- 32kword 112 a0000h- affffh 50000h- 57fffh 32kword 10 2c0000h- 2cffffh 160000h- 167fffh 32kword 44 4e0000h- 4effffh 270000h- 277fffh 32kword 78 6f0000h- 6fffffh 378000h- 37ffffh 32kword 111 90000h- 9ffffh 48000h- 4ffffh 32kword 9 2b0000h- 2bffffh 158000h- 15ffffh 32kword 43 4d0000h- 4dffffh 268000h- 26ffffh 32kword 77 6e0000h- 6effffh 370000h- 377fffh- 32kword 110 80000h- 8ffffh 40000h- 47fffh 32kword 8 2a0000h- 2affffh 150000h- 157fffh 32kword 42 4c0000h- 4cffffh 260000h- 267fffh 32kword 76 6d0000h- 6dffffh 368000h- 36ffffh 32kword 109 70000h- 7ffffh 38000h- 3ffffh 32kword 7 290000h- 29ffffh 148000h- 14ffffh 32kword 41 4b0000h- 4bffffh 258000h- 25ffffh 32kword 75 6c0000h- 6cffffh 360000h- 367fffh- 32kword 108 60000h- 6ffffh 30000h- 37fffh 32kword 6 280000h- 28ffffh 140000h- 147fffh 32kword 40 4a0000h- 4affffh 250000h- 257fffh 32kword 74 6b0000h- 6bffffh 358000h- 35ffffh 32kword 107 50000h- 5ffffh 28000h- 2ffffh 32kword 5 270000h- 27ffffh 138000h- 13ffffh 32kword 39 490000h- 49ffffh 248000h- 24ffffh 32kword 73 6a0000h- 6affffh 350000h- 357fffh- 32kword 106 40000h- 4ffffh 20000h- 27fffh 32kword 4 260000h- 26ffffh 130000h- 137fffh 32kword 38 480000h- 48ffffh 240000h- 247fffh 32kword 72 690000h- 69ffffh 348000h- 34ffffh 32kword 105 30000h- 3ffffh 18000h- 1ffffh 32kword 3 250000h- 25ffffh 128000h- 12ffffh 32kword 37 470000h- 47ffffh 238000h- 23ffffh 32kword 71 680000h- 68ffffh 340000h- 347fffh- 32kword 104 20000h- 2ffffh 10000h- 17fffh 32kword 2 240000h- 24ffffh 120000h- 127fffh 32kword 36 460000h- 46ffffh 230000h- 237fffh 32kword 70 670000h- 67ffffh 338000h- 33ffffh 32kword 103 10000h- 1ffffh 08000h- 0ffffh 32kword 1 230000h- 23ffffh 118000h- 11ffffh 32kword 35 450000h- 45ffffh 228000h- 22ffffh 32kword 69 660000h- 66ffffh 330000h- 337fffh- 32kword 102 00000h- 0ffffh 00000h- 07fffh 32kword 0 220000h- 22ffffh 110000h- 117fffh 32kword 34 440000h- 44ffffh 220000h- 227fffh 32kword 68 a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) a21-a-1 (byte mode) a21-a0 (word mode) bank(iv) bank(iv) bank(iii) bank(ii) bank(i) bank(iii) bank(iii)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 10 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory bus operation 1) x can be vih or vil for control pins. 2) x at ry/by# is v ol or v oh(hi - z) . the ry/by# is an open drain output pin and indicates status of t he internal wsm.when low, it indicates that the wsm is busy performing an operation. a pull - up resistor of 10k - 100k ohms is required to allow the ry/by# signal to transition h igh indicating a ready wsm condition. ce# oe# we# rp# dq0-15* ry/by# array vil vil vih vih data output v oh(hi-z) status register vil vil vih vih status register data x 2) identifier code vil vil vih vih identifier code v oh(hi-z) page vil vil vih vih data output v oh(hi-z) vil vih vih vih high-z x 2) program vil vih vil vih command/data in x 2) erase vil vih vil vih command x 2) others vil vih vil vih command x 2) vih x 1) x 1) vih high-z x 2) x 1) x 1) x 1) vil high-z v oh(hi-z) deep power down stand by read write output disable mode pins * in case of byte(x8) organization, dq8 - dq15 is ignored.
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 11 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory software command definition command list (wp# =vih or vil) 1) in the case of word mode(byte#=vih), upper byte data (dq15 - dq8) is ignored. 2) wa=write address, wd=write data 3) wa0, wan=write address, wd0, wdn=write data. word mode (byte#=vih) : write address and write data must be provided sequentially fr om 00h to 7fh for a6 - a0. page size is 128 words (128 - word x 16 - bit), and also a21 - a7 (block address, page address) must be valid. byte mode (byte#=vil) : write address and write data must be provided sequentially fr om 00h to ffh for a6 - a - 1. page size is 256 bytes (256 - byte x 8 - bit), and also a21 - a7 (block address, page address) must be valid. 4) wa=write address: a21 - a7 (block address, page address) must be valid. 5) ba=block address : a21 - a12[bank(i)], a21 - a15 [bank(ii), bank(iii), bank(iv)] 6) ra=read address: a21 - a7 (block address, page address) must be valid. command list (wp# =vih) data 1) data data (dq0-15),(dq0-7) (dq0-15),(dq0-7) (dq0-15),(dq0-7) word/byte program write bank 40h write wa 2) wd 2) page program write bank 41h write wa0 3) wd0 3) write wan 3) wdn 3) page buffer to flash write bank 0eh write wa 4) d0h 1) block erase/confirm write bank 20h write ba 5) d0h 1) erase all unlocked blocks write x a7h write x d0h 1) clear page buffer write x 55h write x d0h 1) single data load to page buffer write bank 74h write wa wd flash to page buffer write bank f1h write ra 6) d0h 1) command 1st bus cycle mode address 2nd bus cycle mode address 3rd-129th bus cycles(word mode) 3rd-257th bus cycles(byte mode) mode address data 1) data data (dq0-15) a21-a18 a0 (dq0-15) (dq0-15) read array write x ffh page read write x f3h read rd0 5) read sa+i 6) rdi 6) device identifier write bank 2) 90h read bank 2) ia 3) id 3) read status register write bank 2) 70h read srd 4) clear status register write x 50h suspend write bank 2) b0h resume write bank 2) d0h sa 5) bank 2) command 1st bus cycle mode address 2nd bus cycle 3rd-5th bus cycles mode address mode address 1) in the case of word mode(byte#=vih), upper byte data (dq15 - dq8) is ignored. 2) bank=bank address (bank(i) - bank(iv): a21 - 18) 3) ia=id code address: a0=vil (manufacturer ? s code): a0=vih (device code), id=id code 4) srd=status register data 5) sa=a21 - a2:1 st page address, a1,a0:voluntary address / rd0=1 st page read data 6) sa+i: page address(is equal to 1 st page address of a21 - a2), a1,a0: voluntary address / rdi: 2 nd page read data
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 12 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory data 1) data 1) data 1) (dq0-15/dq0-7) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank 60h write bank block 6) write bank ach page program write bank 60h write bank block 6) write bank ach page buffer to flash write bank 60h write bank block 6) write bank ach block erase/confirm write bank 60h write bank block 6) write bank ach clear page buffer write bank 60h write bank block 6) write bank ach single data load to page buffer write bank 60h write bank block 6) write bank ach flash to page buffer write bank 60h write bank block 6) write bank ach data 1) data 1) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank block# 6) write bank 7bh page program write bank block# 6) write bank 7bh page buffer to flash write bank block# 6) write bank 7bh block erase/confirm write bank block# 6) write bank 7bh clear page buffer write bank block# 6) write bank 7bh single data load to page buffer write bank block# 6) write bank 7bh flash to page buffer write bank block# 6) write bank 7bh data 1) data data (dq0-15/dq0-7) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank 40h write wa 2) wd 2) page program write bank 41h write wa0 3) wd0 3) write wan 3) wdn 3) page buffer to flash write bank 0eh write wa 4) d0h 1) block erase/confirm write bank 20h write ba 5) d0h 1) clear page buffer write x 55h write x d0h 1) single data load to page buffer write bank 74h write wa wd flash to page buffer write bank f1h write ra 7) d0h 1) 1st bus cycle mode address 2nd bus cycle address 3rd bus cycle mode address mode address setup command for software lock release setup command for program or erase operations 6th bus cycle 7th bus cycle setup command for software lock release 4th bus cycle 5th bus cycle mode address mode 8th-134th bus cycles(word mode) 8th-262th bus cycles(byte mode) mode address mode address mode address 7) ra=read address: a21 - a7 (block address, page address) must be valid. command list (wp# =vil) software command definition software lock release operation needs following consecutive 7bus cycles.moreover, additional 127(255) bus cycles are needed for page program operation. address dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 block fixed 0 a21 a20 a19 a18 a17 a16 a15 block# fixed 0 a21# a20# a19# a18# a17# a16# a15# 1 ) in the case of word mode(byte#=vih) upper byte data (dq15 - dq8) is ignored. 2) wa=write address, wd=write data 3) wa0, wan=write address, wd0, wdn=write data. write address an d write data must be provided sequentially from 00h to 7fh for a6 - a0(word mode) and from 00h to ffh for a6 - a - 1(byte mode), respectively. page size is 128 words (128 - word x 16 - bit/ word mode) or page size is 256 bytes (256 - word x 8 - bit/ byte mode), and also a21 - a7 (block address, page address) must be valid. 4) wa=write address: a21 - a7 (block address, page address) must be valid. 5) ba=block address : a21 - a12[bank(i)], a21 - a15 [bank(ii), bank(iii), bank(iv)] 6) block=block address: a21 - a15, block#=a21# - a15#
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 13 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block locking wp# pin must not be switched during performing read / write oper ations or wsm busy (wsms=0). status register bank(ii) bank(iii) bank(iv) boot parameter/main main main main vil x locked locked locked locked locked deep power down mode vih unlocked unlocked unlocked unlocked unlocked all blocks unlocked locked locked all blocks locked(valid to operate software lock release) write protection provided notes bank(i) locked locked locked rp# wp# vih vil "1" "0" s.r. 7 (dq7) write state machine status ready busy s.r. 6 (dq6) suspend status suspended operation in progress/completed s.r. 5 (dq5) erase status error successful s.r. 4 (dq4) program status error successful s.r. 3 (dq3) block status after erase error successful s.r. 2 (dq2) reserved - - s.r. 1 (dq1) reserved - - s.r. 0 (dq0) reserved - - symbol (i/o pin) status definition
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 14 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory min. typ. 1) max. ili input leakage current -1 1 a ilo output leakage current -10 10 a isb3 5 25 a vcc = 3.6v, vin = vil/vih, f-rp# = oe# = vih, 5mhz 20 30 ma f-ce# =vil, iout = 0ma 1mhz 4 8 ma icc1p vcc page read current vcc = 3.6v, vin = vil/vih, f-rp# = oe# = vih, f-ce# =vil, iout = 0ma 5mhz 5 10 ma vil input low voltage -0.5 0.4 v vih input high voltage 2.4 vcc+0.5 v vol output low voltage 0.45 v voh1 0.85xvcc v voh2 vcc-0.4 v vlko low vcc lock out voltage 2) 1.5 2.2 v iol = 4.0ma output high voltage ioh = -2.0ma ioh = -100ua 200 a icc5 vcc suspend current vcc = 3.6v, vin = vil/vih, f-ce#= f-rp# = f- wp# = vih 35 ma icc4 vcc erase current vcc = 3.6v, vin = vil/vih, f-ce#= f-rp# = f- wp# = vih 35 ma icc3 vcc program current vcc = 3.6v, vin = vil/vih, f-ce#= f-rp# = f- wp# = vih 15 ma icc1 vcc read current for word icc2 vcc write current for word vcc = 3.6v, vin = vil/vih, f-rp# = oe# = vih, f- ce# = we# = vil isb4 vcc= 3.6v, vin= gnd or vcc, f-rp#= gnd 0.3v 0.1 vcc deep power down current vcc= 3.6v, vin= vil/vih, f-rp#= vil 6 a units 0v < vin < vcc 0v < vout < vcc 6 a isb2 vcc= 3.6v, vin= gnd/vcc, f-ce#= f-rp#= f-wp#= vcc0.3v 0.1 vcc stand by current symbol parameter test conditions limits device id code absolute maximum ratings dc electrical characteristics a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex. data manufacturer code vil "0" "0" "0" "1" "1" "1" "0" "0" 1ch device code (top boot) vih "1" "0" "1" "1" "1" "0" "0" "0" b8h device code (bottom boot) vih "1" "0" "1" "1" "1" "0" "0" "1" b9h code pins ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted) the output of upper byte data (dq15 - dq8) is ? 0h ? . 1) minimum dc voltage is ? 0.6v on input / output pins. during transitions, the level may u ndershoot to ? 2.0v for periods <20ns. maximum dc voltage on input / output pins is vcc+0.5v wh ich, during transitions, may overshoot to vcc+1.5v for periods <20ns. all currents are in rms unless otherwise noted. 1) typical values at flash vcc=3.3v, ta=25 c . 2) to protect against initiation of write cycle during flash vcc power up / down, a write cycle is locked out for flash vcc less than vlko. if flash vcc is less than vlko, write state machine is reset to read mode. when the write state machine is in busy state, if fl ash vcc is less than vlko, the alteration of memory contents ma y occur. symbol parameter conditions min. max. units vcc vcc voltage -0.2 4.6 v vi1 all input or output voltage 1) -0.6 4.6 v ta ambient temperature -40 85 c tbs temperature under bias -50 95 c tstg storage temperature -65 125 c iout output short circuit current 100 ma with respect to gnd
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 15 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac electrical characteristics - timing measurements are made under ac waveforms for read operati ons. read only mode min. typ. max. trc tavav read cycle time 70 ns ta(ad) tavqv address access time 70 ns ta(ce) telqv chip enable access time 70 ns ta(oe) tglqv output enable access time 30 ns ta(pad) tpavqv page read access time 25 ns tceph ce# "h"pulse width 30 ns tclz telqx chip enable to output in low-z 0 ns tdf(ce) tehqz chip enable high to output in high-z 25 ns tolz tglqx output enable to output in low-z 0 ns tdf(oe) tghqz output enable to high to output in high-z 25 ns tphz tplqz rp# low to output high-z 150 ns ta(byte) tfl/hqv byte# access time 70 ns tbhz tflqz byte# low to output high-z 25 ns toh toh output hold from ce#, oe# and addresses 0 ns tbcd telfl/h ce# low to byte# high or low 5 ns tbad tavfl/h address to byte# high or low 5 ns toeh twhgl oe# hold from we# high 10 ns tps tphel rp# recovery to ce# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 16 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory - timing measurements are made under ac waveforms for read operati ons. - typical values at flash vcc=3.3v and ta=25 c . read / write mode (ce# control) ac electrical characteristics ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted) - read timing parameters during command write operations mode are the same as during read only operation mode. - typical values at flash vcc=3.3v and ta=25 c . read / write mode (we# control) min. typ. max. twc tavav write cycle time 70 ns tas tavwh address setup time 35 ns tah twhax address hold time 0 ns tds tdvwh data setup time 35 ns tdh twhdx data hold time 0 ns toeh twhgl oe# hold from we# high 10 ns tcs telwl chip enable setup time 0 ns tch twheh chip enable hold time 0 ns twp twlwh write pulse width 35 ns twph twhwl write pulse width high 30 ns tbs tfl/hwh byte enable high or low set-up time 35 ns tbh twhfl/h byte enable high or low hold time 70 ns tghwl tghwl oe# hold to we# low 0 ns tbls tphhwh block lock setup to write enable high 70 ns tblh tqvph block lock hold from valid srd 0 ns tdap twhrh1 duration of auto program operation(word mode) 30 300 s tdap twhrh1 duration of auto program operation(byte mode) 30 300 s tdap twhrh1 duration of auto program operation(page mode) 4 80 ms tdae twhrh2 duration of auto block erase operation 150 600 ms twhrl twhrl delay time during internal operation 70 ns tps tphwl rp# recovery to ce# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v min. typ. max. twc tavav write cycle time 70 ns tas taveh address setup time 35 ns tah tehax address hold time 0 ns tds tdveh data setup time 35 ns tdh tehdx data hold time 0 ns toeh tehgl oe# hold from ce# high 10 ns tws twlel write enable setup time 0 ns twh tehwh write enable hold time 0 ns tcep teleh ce# pulse width 35 ns tceph tehel ce#"h" pulse width 30 ns tbs tfl/heh byte enable high or low set-up time 35 ns tbh tehfl/h byte enable high or low hold time 70 ns tghel tghel oe# hold to ce# low 0 ns tbls tphheh block lock setup to write enable high 70 ns tblh tqvph block lock hold from valid srd 0 ns tdap tehrh1 duration of auto program operation(word mode) 30 300 s tdap tehrh1 duration of auto program operation(byte mode) 30 300 s tdap tehrh1 duration of auto program operation(page mode) 4 80 ms tdae tehrh2 duration of auto block erase operation 150 600 ms tehrl tehrl delay time during internal operation 70 ns tps tphel rp# recovery to ce# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 17 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory during power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. the device must be protected against initiation of write cycle f or memory contents during power up / down. the delay time of min. 60 sec is always required before read operation or write operation is initiated from the time flash vcc reaches flash vcc min. during power up /down. by holding rp#=vil, the co ntents of memory is protected during flash vcc power up / down. during power up, rp# must be held vil for min. 2 s from the time flash vcc reaches flash vcc min.. during power down, rp# must be held vil until flash vcc reaches gnd. rp# doesn ? t have latch mode, therefore rp# must be held vih during read operation or erase / program operat ion. parameter min. typ. max. unit block erase time 150 600 ms main block write time 1 4 sec page write time 4 80 ms flash to page buffer time 100 150 s parameter min. typ. max. unit program susupend time 15 s erase susupend time 15 s symbol parameter min. typ. max. unit tvcs f-rp#=vih setup time from flash vcc min. 2 s tvhel f-ce#=vil setup time from flash vcc min. 60 s flash vcc power up / down timing program suspend / erase suspend time program / erase time
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 18 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory flash vcc power up / down timing ac waveforms for read operation and test conditions t ps 3.0v gnd v cc v ih rp# read /write inhibit t vcs ce# we# read /write inhibit v il v ih v il v ih v il t ps read /write inhibit t vhel output valid address ce# oe# we# data address valid high-z rp# v ih v il t a(ad) t a(ce) v ih v il v ih v il t df(ce) t df(oe) v ih v il t oeh t a(oe) t oh high-z t olz t clz t phz v oh v o v ih v il t ps t rc a21-a0 input voltage : v il =0v, v ih =flash vcc input rise and fall times : < 5ns reference voltage at timing measurement : (flash vcc)/2 output load : 1 ttl gate + cl(30pf) or dut 3.3kohm 1n914 1.3v cl=30pf test conditions for ac characteristics - after inputting read array ffh, it is necessary to make f - ce# ? h ? pulse more than 30ns (tceph). and after inputting read array command ffh, it is also necessa ry to keep 30ns to recover before starting read after we# rises ? h ? in case of changing address(es) and f - ce#= ? l ? .
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 19 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory word/byte ac waveforms for read operation address a21-a0 ce# oe# byte# data d7-d0 address valid high-z v ih v il t a(ad) t a(ce) v ih v il v ih v il t df(ce) t df(oe) v ih v il t a(oe) output valid t oh t olz t clz v oh v ol t a(byte) t bcd t bad data d14-d8 v oh v ol high-z t bad t a(byte) t bhz t a(ad) valid valid valid d15/a-1 address valid v ih v il d15 a-1 address valid when byte# = vih, ce# = oe# = vil, d15/a - 1 is output status. at this time, input signal must not be appl ied. ac waveforms for page read operation a 21 - a 2 v ih v il 1st address f-ce# v ih v il we# v ih v il v ih v il high-z data f3h page address valid v ih v il a 1 - a 0 t a(ce) address valid(voluntary address) oe# v ih v il t a(ad) t a(oe) t a(oe) valid t a(pad) valid valid t a(pad) valid t a(pad) 2nd 3rd 4th t ceph - after inputting page read command f3h, it is necessary to make f - ce# ? h ? pulse more than 30ns (tceph). and after inputting page read command f3h, it is also necessar y to keep 30ns to recover before starting read after we# rises ? h ? in case of changing address(es) and f - ce#= ? l ? . - once page read mode is valid, the mode is kept until f - rp# is set to vil or the chip is powered off.
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 20 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory address a21-a0 bank address valid v ih v il address valid program read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd ffh v ih v il rp# v ih v il wp# t ps t ws t bls t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t dap t blh t a(oe) t a(ce) v ih v il byte# t bs t bh v oh v ol ry/by# address a21-a0 bank address valid v ih v il address valid program read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd ffh v ih v il rp# v ih v il wp# t ps t cs t bls t ch t wp t wc t ah t as t oeh t dh t ds t dap t a(oe) t a(ce) t wph v ih v il byte# t bs t bh t whrl t blh v oh v ol ry/by# ac waveforms for word/byte program operation (we# control) ac waveforms for word/byte program operation (ce# control)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 21 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory \ a21-a7 bank address valid v ih v il address valid read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din dout ffh v ih v il rp# v ih v il wp# t ps t bls t wc t dap t blh the other bank address valid v ih v il address 00h 01h-feh ffh valid din din srd t as t ah t cs t ch t wp t wph t dh t ds t oeh t a(ce) t a(oe) t ghwl t oeh t whrl t a(ce) t a(oe) valid byte#=vil (a 6 -a -1 ) byte#=vih (a 6 -a 0 ) byte# v ih v il t bs t bh v oh v ol ry/by# 00h 01h-7eh 7fh v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din dout ffh v ih v il rp# v ih v il wp# t ps t bls t wc t dap t blh v ih v il din din srd t as t ah t ws t wh t cep t ceph t dh t ds t oeh t a(ce) t a(oe) t ghel t oeh t ehrl t a(ce) t a(oe) a21 - a7 bank address valid address valid read status register write read array command the other bank address valid address valid byte#=vil (a 6 -a -1 ) byte#=vih (a 6 -a 0 ) byte# v ih v il t bs t bh v oh v ol ry/by# bank address valid 00h 01h-feh ffh valid 00h 01h-7eh 7fh ac waveforms for page program operation (ce# control) ac waveforms for page program operation (we# control)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 22 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory address a21-a0 v ih v il erase ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd ffh v ih v il rp# v ih v il wp# t ps t ws t bls t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t dae t blh t a(oe) t a(ce) bank address valid address valid read status register write read array command bank address valid byte# t bs t bh v ih v il v oh v ol ry/by# t ceph address a21-a0 bank address valid v ih v il address valid erase read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd ffh v ih v il rp# v ih v il wp# t ps t cs t bls t ch t wp t wc t ah t as t oeh t dh t ds t dae t blh t a(oe) t a(ce) t wph byte# t bs t bh v ih v il v oh v ol t whrl ry/by# ac waveforms for erase operation (we# control) ac waveforms for erase operation (ce# control)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 23 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory v ih v il valid read status register read array in the other bank ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd t cs t ch t wp t wc t ah t as t oeh t ds t a(oe) t a(ce) t wph address a21 - a7 bank address valid v ih v il address valid valid program in a bank bank address change valid valid valid dout dout t dh byte#=vil (a6-a-1) byte#=vih (a6-a0) t whrl ry/by# v oh v ol ac waveforms for word/byte program operation with bgo (we# contr ol) v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd t ws t wh t cep t wc t ah t as t oeh t dh t ds t a(oe) t a(ce) v ih v il address a21 - a7 dout dout valid read status register read array in the other bank bank address valid address valid valid program in a bank bank address change valid valid valid byte#=vil (a6-a-1) byte#=vih (a6-a0) v oh v ol ry/by# t ehrl ac waveforms for word/byte program operation with bgo (ce# contr ol)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 24 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory \ a21-a7 bank address valid v ih v il address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din srd t wc v ih v il address din din t as t ah t cs t ch t wp t wph t dh t ds t oeh t whrl t a(ce) t a(oe) read array in the other bank valid bank address change valid valid valid program in a bank dout dout byte#=vil (a6-a-1) byte#=vih (a6-a0) ry/by# v oh v ol 00h 01h-feh ffh 00h 01h-7eh 7fh ac waveforms for page program operation with bgo (we# control) tdh v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din srd t wc v ih v il din din t as t ah t ws t wh t cep t ceph t dh t ds t oeh t a(ce) t a(oe) a21 - a7 address dout dout address valid read array in the other bank valid bank address change valid valid valid program in a bank bank address valid byte#=vil (a6-a-1) byte#=vih (a6-a0) t ehrl v oh v ol ry/by# 00h 01h-feh ffh 00h 01h-7eh 7fh ac waveforms for page program operation with bgo (ce# control)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 25 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory address bank address valid v ih v il address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd t cs t ch t wp t wc t ah t as t oeh t dh t ds t a(oe) t a(ce) t wph dout dout valid valid read status register read array in the other bamk progtam in a bank bank address change ry/by# v oh v ol t whrl ac waveforms for erase operation with bgo (we# control) address v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd t ws t wh t cep t wc t ah t as t oeh t dh t ds t a(oe) t a(ce) dout dout bank address valid address valid valid valid read status register read array in the other bamk progtam in a bank bank address change ry/by# t ehrl v oh v ol ac waveforms for erase operation with bgo (ce# control)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 26 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for suspend operation (we# control) ac waveforms for suspend operation (ce# control) address a 21 - a 0 v ih v il bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data b0h srd valid v ih v il rp# v ih v il wp# t cs t ch t wp t ah t as t oeh suspend time t blh t a(oe) t a(ce) bank address valid s.r.6,7=1 read status register ry/by# v oh v ol address a 21 - a 0 v ih v il bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data b0h srd valid v ih v il rp# v ih v il t ah t as t oeh suspend time t blh t a(oe) t a(ce) bank address valid s.r.6,7=1 read status register t ws t wh t cep ry/by# wp# v oh v ol
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 27 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for device id read operation with bbr(back bank read) v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 90h t cs t wp t wc t a(oe) t a(ce) change bank address id return bank address t ch t a(ad) t a(oe) dout t a(ad) t a(oe) id t a(ad) t a(ce) t a(ce) bank address valid address valid address valid bank address valid address a 21 - a 0 v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 70h t cs t wp t a(oe) t a(ce) bank address valid change bank address address valid srd return bank address t ch t ehrl t a(oe) dout t a(ad) t a(oe) t a(ce) t a(ce) srd t a(ad) bank address valid address a 21 - a 0 ac waveforms for status register read operation with bbr(back bank read)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 28 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory word/byte program flow chart block erase flow chart page program flow chart status register check flow chart start write 40h write address, data status register read sr.7 = 1? full status check if desired word program completed write boh? no yes no suspend loop write d0h yes yes start write 41h n = 0 write address n, data n sr.7 = 1? full status check if desired page program completed write boh? no yes no suspend loop write d0h yes yes n = n + 1 n = 7fh?(word) n = ffh?(byte) no yes status register read start write 20h write d0h block address sr.7 = 1? full status check if desired erase completed write boh? no yes no suspend loop write d0h yes yes status register read start sr.3 = 0? no yes sr.4,5 = 1? no yes sr.5 = 0? no yes sr.4 = 0? no yes pass (block erase, program) command sequence error block erase error program error (page program) block erase error (block fail)
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 29 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory single data load to page buffer flow chart suspend / resume flow chart clear page buffer flow chart page buffer to flash flow chart start write 74h write address, data load finished? single data load to page buffer completed no yes start write b0h status register read s.r. 7=1? no yes write ffh read array data read finished? operation restart no yes s.r. 6=1? no yes write d0h erase/ program finished suspend resume start write 0eh write d0h page address sr.7 = 1? full status check if desired page buffer to flash completed write boh? no yes no suspend loop write d0h yes yes status register read start write 55h write d0h clear page buffer completed
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 30 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory operation status (wp#=vih) read status register ffh ffh 90h read/standby state (random read mode) 70h clear status register 50h read array (random read) change bank address erase all unlocked blocks setup block erase setup word program setup page program setup page buffer to flash setup flash to page buffer setup single data load to page buffer setup clear page buffer setup d0h 55h 74h wd f1h 0eh 41h 40h a7h erase & verify read status register program & verify read status register d0h wdi i=0-127 wd d0h setup state internal state d0h ready read status register suspend state d0h d0h b0h b0h other others 90h 70h 20h read array (random read) read device identifier read array (random read) ffh 70h others 3) d0h change bank address read state with bgo change bank address read array (random read) read array (random read) read state with bgo back bank read state 1) in case of page read, f3h is used instead of ffh in operation st atus (f - wp#=vih). 2) once page read mode is set, page read mode is kept until powe r off or f - rp# is set to vil. 3) after setting up clear page buffer, d0h enables to clear page buffer. 4) to access any bank during erase all unlocked block results s tatus register read. although read status register command and read array command can be issued under suspend state, output data make no sense.
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 31 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory operation status (wp#=vil) change bank address read status register ffh ffh 90h read/standby state (random read mode) 70h clear status register 50h read array (random read) change bank address block erase setup word program setup page program setup page buffer to flash setup flash to page buffer setup single data load to page buffer setup clear page buffer setup d0h 55h 74h wd f1h 0eh 41h 40h erase & verify read status register program & verify read status register d0h wdi i=0-127 wd d0h setup state internal state ready 70h read status register suspend state d0h d0h b0h b0h read state with bgo other other 90h 70h 20h read array (random read) read device identifier change bank address read array (random read) ffh read array (random read) software lock release setup software lock release setup software lock release setup software lock release setup software lock release setup others 60h ba 3) ach ba# 3) 7bh others others others 4) others d0h read array (random read) read state with bgo back bank read state read array (random read) change bank address 1) in case of page read, f3h is used instead of ffh in operation st atus (f - wp#=vil). 2) once page read mode is set, page read mode is kept until powe r off or f - rp# is set to vil. 3) ba, ba#: block address, block address# (shown in command list (f - wp#=vil) in detail). 4) after setting up clear page buffer, d0h enables to clear page buffer.
m5m29kb/t641avp renesas lsis rev.1.3_48a_bezz 32 67,108,864 - bit (8,388,608 - word by 8 - bit /4,194,304 - word by 16 - bit) cmos 3.3v - only, block erase flash memory 48 p3r - c package dimension
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